1. Field of Invention
The present general inventive concept relates to the preparation of silicon-based semiconductor materials.
2. Description of the Related Art
The vast majority of wafers for solar cells for photovoltaic devices are made by processes which add substantial costs and impart defects that significantly reduce performance. Virtually all wafers are made by “wire sawing” wafers from larger ingots or blocks of silicon. The wire sawing has several defects and cost and yield elements. The vibration in the wire sawing action causes micro-cracks in the wafer which diminishes efficiency, causes downstream failure from subsequent cracking; these micro cracks are typically 15-25 microns deep from both sides. As the wafer is processed in downstream in line processing and assembly and shipping these stresses can put a moment on the crack and propagate a crack, which is especially costly as value is added to the wafer as a cell, as a module and even as it is installed making this defect very expensive. The wire sawing is expensive in labor and in expendables and amortization of expensive equipment. The “yield losses” of silicon from the wire sawing, including the cleaning of the ingot, the machining of the “loaves” and the losses from wire sawing often approach or exceed 70%. The inescapable micro cracks limit how thin the wafers can be made, thus forcing the industry to use wafers thicker than otherwise desired.
Virtually all the ingots prepared for machining are made by one of two processes. Multigrain silicon ingots made by melting silicon in crucibles constructed of rebonded fused silica. These rebonded fused silica crucibles are fabricated from glass quality silica sand containing 350 ppm Fe2O3. The sand is melted and then ground slip cast into the desired shape and the rebonded, thus putting the Fe2O3 into solution. The crucible is then filled with lumps of solar grade silicon, 7-9 nines pure, and melted in a furnace in a vacuum with a low grade vacuum and kept at temperature for about 56 hours. During this time about 80% of the volume of silica in the crucible transforms from amorphous silica to a crystalline form called cristobalite, the cristobalite precipitating in a pure form and thus zone refining the now iron rich glass into the grain boundaries which flows and rapidly defuses throughout the silicon melt. As well, the silicon steals oxygen from the crucible, and carbon monoxide in the atmosphere reacts with the silicon as well. This results in much reduced efficiency in the resulting solar cells along with a large volume of silicon cleaned from all surfaces because of the contamination therein from carbon and oxygen.
Single crystal ingots made by the Czochralski process by drawing a crystal from a liquid pool of silicon held in an essentially pure quartz crucible. The quartz in this case is much purer than the rebonded fuses silica crucible, but there is much more flow of silicon in the crucible resulting in large amounts of oxygen distributed throughout the ingot thus reducing efficiency.
Because of the rates of diffusion in the silicon melts and the length of time at temperature, it is not possible to dope with boron, phosphorous or arsenic and maintain doping precision and accuracy required. For this reason, an N type wafer has not been possible despite its advantages.
For these reasons these technical approaches have been compromised by very low yield on silicon, often 30% or less; very high costs for one use crucibles; high cost from long times and large masses at high temperature; high costs from wire sawing and its associated processes; low yield from downstream and in process failure from micro cracking; low efficiency due to contamination from processing; and an inability to make a very thin wafer.
In the field of fabricating silicon semiconductor wafers, there is a need for methods and processes that increase in yield on silicon to 90% or higher from 30% or lower, maintain very high purity resulting in higher efficiency, and display an ability to make very thin wafers, as thin as less than 50 microns, thus potentially reducing the silicon per wafer by as much as 88% compared to current practices. It is also desirable to eliminate micro cracks and downstream and in process failures, reduce labor and energy costs, and move beyond expensive single-use crucibles.